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LOW POWER |
1 |
A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS |
2 |
A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic ADC |
3 |
A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-μm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration |
4 |
A Dynamic Timing Error Avoidance Technique Using Prediction Logic in High-Performance Designs |
5 |
A Wideband Low-Noise Variable-Gain Amplifier with a 3.4 dB NF and up to 45 dB gain tuning range in 130nm CMOS |
6 |
Analysis, Comparison, and Experimental Validation of a Class AB Voltage Follower With EnhancedBandwidth and Slew Rate |
7 |
Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for PowerReduction |
8 |
Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors |
9 |
Exploiting Algorithmic Noise Tolerance for Scalable On-Chip Voltage Regulation |
10 |
Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip StaticLinearity Test of ADCs |
11 |
Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage forArray Augmentation in 32-nm CMOS |
12 |
Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow-Phase-NoiseCellular Applications |
13 |
Multiloop Control for Fast Transient DC–DC Converter |
14 |
Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application |
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HIGH SPEED AND SIGNAL PROCESSING |
15 |
A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal Common-Mode Control |
16 |
A 2.4-GHz Frequency-Drift-Compensated Phase-Locked Loop With 2.43 ppm/°C Temperature Coefficient |
17 |
A High-Flexible Low-Latency Memory-Based FFT Processor for 4G, WLAN, and Future 5G |
18 |
An Accurate and Noise-Resilient Spread-Spectrum Clock Tracking Aid for Digitally-Controlled Clock andData Recovery Loops |
19 |
An Analog LO Harmonic Suppression Technique for SDR Receivers |
20 |
An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With 0.175μW/Channel in 65-nm CMOS |
21 |
Analysis and Optimization of Multisection Capacitive DACs for Mixed-Signal Processing |
22 |
CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency |
23 |
Design of Reconfigurable Digital IF Filter with Low Complexity |
24 |
Feedforward-Cutset-Free Pipelined Multiply–Accumulate Unit for the Machine Learning Accelerator |
25 |
Line Coding Techniques for Channel Equalization: Integrated Pulse-Width Modulation and ConsecutiveDigit Chopping |
26 |
Multiplier-free Implementation of Galois Field Fourier Transform on a FPGA |
27 |
Power-Efficient Gm-C DSMs With High Immunity to Aliasing, Clock Jitter, and ISI |
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AREA EFFICIENT/ TIMING & DELAY REDUCTION |
28 |
A Combined Arithmetic-High-Level Synthesis Solution to Deploy Partial Carry-Save Radix-8 BoothMultipliers in Datapaths |
29 |
A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories |
30 |
A High-Throughput Hardware Accelerator for Lossless Compression of a DDR4 Command Trace |
31 |
An Energy-efficient Accelerator based on Hybrid CPU-FPGA Devices for Password Recovery |
32 |
Area–Delay–Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data |
33 |
Area-Time Efficient Streaming Architecture for FAST and BRIEF Detector |
34 |
Chaos-Based Bitwise Dynamical Pseudorandom Number Generator on FPGA |
35 |
Efficient Design for Fixed-Width Adder-Tree |
36 |
JPV1936 Hardware-Efficient Post-processing Architectures for True Random Number Generators |
37 |
JPV1937 Multistage Linear Feedback Shift Register Counters With Reduced Decoding Logic in 130-nm CMOS forLarge-Scale Array Applications |
38 |
JPV1938 New Majority Gate Based Parallel BCD Adder Designs for Quantum-dot Cellular Automata |
39 |
JPV1939 Rapid Balise Telegram Decoder with Modified LFSR Architecture for Train Protection Systems |